Resets: The Timing Event You Forgot
Understanding reset timing - recovery, removal, async assert sync deassert, reset trees, and why sporadic startup failures haunt your design
Articles¶
Reference notes on FPGA timing closure, constraints, and verification.
Topics include timing analysis, constraint methodology, and RTL design patterns.
CDC: Two Flip-Flops Are Not Magic
Understanding clock domain crossing - synchronizers, metastability, pulse transfer, gray code, and why 2-flop sync only works for levels
Silicon Real Estate: Your Resource Budget
Understanding FPGA resource utilization - LUTs, registers, BRAM, DSPs, and why 94% utilization means your design won't close timing
Pipelining Without Breaking Your Protocol
Understanding how to add pipeline registers without breaking valid/ready handshakes - skid buffers, register slices, and protocol-correct timing fixes
Understanding Timing Analysis
A deep dive into static timing analysis - understanding slack, path delays, clock skew, and why period minus data path is not your margin
Constraints: The Contract You Forgot to Sign
Understanding FPGA timing constraints - clocks, I/O delays, CDC, and why 'Timing Met' means nothing without proper constraints
Your FPGA Lives a Lifetime While You Blink
Understanding FPGA timing at 156.25 MHz - where half a nanosecond means the difference between working and failing